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M 25AA040/25LC040/25C040
4K SPITM Bus Serial EEPROM
Max Clock Frequency 1 MHz 2 MHz 3 MHz Temp Ranges C,I C,I C,I,E CS SO WP VSS
DEVICE SELECTION TABLE
Part Number 25AA040 25LC040 25C040 VCC Range 1.8-5.5V 2.5-5.5V 4.5-5.5V
PACKAGE TYPES
PDIP/SOIC 1 25xx040 2 3 4 8 7 6 5 VCC HOLD SCK SI
FEATURES
* Low power CMOS technology - Write current: 3 mA typical - Read current: 500 A typical - Standby current: 500 nA typical * 512 x 8 bit organization * 16 byte page * Write cycle time: 5ms max. * Self-timed ERASE and WRITE cycles * Block write protection - Protect none, 1/4, 1/2, or all of array * Built-in write protection - Power on/off data protection circuitry - Write enable latch - Write protect pin * Sequential read * High reliability - Endurance: 10M cycles (guaranteed) - Data retention: > 200 years - ESD protection: > 4000 V * 8-pin PDIP, SOIC, and TSSOP packages * Temperature ranges supported: - Commercial: (C) 0C to +70C - Industrial: (I) -40C to +85C - Automotive: (E) (25C040) -40C to +125C
TSSOP HOLD VCC CS SO 1 2 3 4 8 7 6 5 SCK SI VSS WP 25xx040
BLOCK DIAGRAM
Status Register HV Generator
EEPROM I/O Control Logic Memory Control Logic X Dec Page Latches Array
DESCRIPTION
The Microchip Technology Inc. 25AA040/25LC040/ 25C040 (25xx040*) is a 4K bit serial Electrically Erasable PROM. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. Also, write operations to the device can be disabled via the write protect pin (WP).
SI SO CS SCK HOLD WP VCC VSS Sense Amp. R/W Control Y Decoder
*25xx040 is used in this document as a generic part number for the 25AA040/25LC040/25C040 devices. SPI is a trademark of Motorola.
(c) 1997 Microchip Technology Inc.
Preliminary
DS21204A-page 1
25AA040/25LC040/25C040
1.0
1.1
ELECTRICAL CHARACTERISTICS
Maximum Ratings*
FIGURE 1-1:
AC TEST CIRCUIT
VCC
Vcc ...................................................................................7.0V All inputs and outputs w.r.t. Vss.................. -0.6V to Vcc+1.0V Storage temperature ....................................... -65C to 150C Ambient temperature under bias..................... -65C to 125C Soldering temperature of leads (10 seconds) ............. +300C ESD protection on all pins.................................................4kV
*Notice: Stresses above those listed under `Maximum ratings' may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability
2.25 K SO 1.8 K 100 pF
1.2
AC Test Conditions
AC Waveform:
TABLE 1-1:
Name CS SO SI SCK WP VSS VCC HOLD
PIN FUNCTION TABLE
Function Chip Select Input Serial Data Output Serial Data Input Serial Clock Input Write Protect Pin Ground Supply Voltage Hold Input
VLO = 0.2V VH I = VCC - 0.2V VH I = 4.0V Input Output Note 1: For VCC 4.0V 2: For VCC > 4.0V (Note 1) (Note 2) 0.5 VCC 0.5 VCC
Timing Measurement Reference Level
TABLE 1-2:
DC CHARACTERISTICS
Commercial (C): TAMB = 0C to +70C Industrial (I): TAMB = -40C to +85C Automotive (E): TAMB = -40C to +125C VCC = 1.8V to 5.5V VCC = 1.8V to 5.5V VCC = 4.5V to 5.5V (25C040 only)
All parameters apply over the specified operating ranges unless otherwise noted.
Parameter High level input voltage Low level input voltage Low level output voltage High level output voltage Input leakage current Output leakage current Internal Capacitance (all inputs and outputs)
Symbol VIH1 VIH2 VIL1 VIL2 VOL VOL VOH ILI ILO CINT ICC Read
Min 2.0 0.7 VCC -0.3 -0.3 -- -- VCC -0.5 -10 -10 -- -- -- -- -- -- --
Max VCC+1 VCC+1 0.8 0.3 VCC 0.4 0.2 -- 10 10 7 1 500 5 3 5 2
Units V V V V V V V A A pF mA A mA mA A A
Test Conditions VCC 2.7V (Note) VCC< 2.7V (Note) VCC 2.7V (Note) VCC < 2.7V (Note) IOL = 2.1 mA IOL = 1.0 mA, VCC < 2.5V IOH =-400 A CS = VCC, VIN = VSS TO VCC CS = VCC, VOUT = VSS TO VCC TAMB = 25C, CLK = 1.0 MHz, VCC = 5.0V (Note) VCC = 5.5V; FCLK=3.0 MHz; SO = Open VCC = 2.5V; FCLK=2.0 MHz; SO = Open VCC= 5.5V VCC = 2.5V CS = Vcc = 5.5V, Inputs tied to VCC or VSS CS = Vcc = 2.5V, Inputs tied to VCC or VSS
Operating Current
ICC Write ICCS
Standby Current
Note: This parameter is periodically sampled and not 100% tested.
DS21204A-page 2
Preliminary
(c) 1997 Microchip Technology Inc.
25AA040/25LC040/25C040
TABLE 1-3: AC CHARACTERISTICS
Commercial (C): Industrial (I): Automotive (E): Symbol FCLK Tamb = 0C to +70C Tamb = -40C to +85C Tamb = -40C to +125C Min -- -- -- 100 250 500 150 250 475 500 30 50 50 50 100 100 -- -- 150 250 475 150 250 475 50 50 -- -- -- 0 -- -- -- 100 100 200 100 100 200 100 150 200 100 150 200 -- 10M Max 3 2 1 -- -- -- -- -- -- -- -- -- -- -- -- -- 2 2 -- -- -- -- -- -- -- -- 150 250 475 -- 200 250 500 -- -- -- -- -- -- -- -- -- -- -- -- 5 -- VCC = 1.8V to 5.5V VCC = 1.8V to 5.5V VCC = 4.5V to 5.5V (25C040 only) Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms E/W Cycles (Note 2) VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V (Note 1) VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 4.5V (Note 1) VCC = 1.8V to 2.5V (Note 1) VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 4.5V (Note 1) VCC = 1.8V to 2.5V (Note 1) VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V (Note 1) (Note 1) VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V Test Conditions VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V All parameters apply over the specified operating ranges unless otherwise noted. Parameter Clock Frequency
CS Setup Time
TCSS
CS Hold Time
TCSH
CS Disable Time Data Setup Time
TCSD TSU
Data Hold Time
THD
CLK Rise Time CLK Fall Time Clock High Time
TR TF THI
Clock Low Time
TLO
Clock Delay Time Clock Enable Time Output Valid from Clock Low Output Hold Time Output Disable Time
TCLD TCLE TV
THO TDIS
HOLD Setup Time
THS
HOLD Hold Time
THH
HOLD Low to Output High-Z
THZ
HOLD High to Output Valid
THV
Internal Write Cycle Time Endurance Note 1: 2:
TWC --
This parameter is periodically sampled and not 100% tested. This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip's BBS or website.
(c) 1997 Microchip Technology Inc.
Preliminary
DS21204A-page 3
25AA040/25LC040/25C040
FIGURE 1-2:
CS
THS THH THS THH
HOLD TIMING
SCK
THZ THV
SO
n+2
n+1
n
high impedance
n
TSU
n-1
SI HOLD
n+2
n+1
n
don't care
n
n-1
FIGURE 1-3:
SERIAL INPUT TIMING
TCSD
CS TCSS Mode 1,1 SCK Mode 0,0 Tsu SI MSB in THD LSB in TR TF TCSH
TCLE TCLD
SO
high impedance
FIGURE 1-4:
CS
SERIAL OUTPUT TIMING
TCSH
THI
TLO
Mode 1,1 Mode 0,0
SCK TV THC SO MSB out TDIS ISB out
SI
don't care
DS21204A-page 4
Preliminary
(c) 1997 Microchip Technology Inc.
25AA040/25LC040/25C040
2.0
2.1
PIN DESCRIPTIONS
Chip Select (CS)
2.5
Write Protect (WP)
A low level on this pin selects the device. A high level deselects the device and forces it into standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go in standby mode as soon as the programming cycle is complete. As soon as the device is deselected, SO goes to the high impedance state, allowing multiple parts to share the same SPI bus. A low to high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated.
This pin is a hardware write protect input pin. When WP is low, all writes to the array or status register are disabled, but any other operation functions normally. When WP is high, all functions, including non-volatile writes operate normally. WP going low at any time will reset the write enable latch and inhibit programming, except when an internal write has already begun. If an internal write cycle has already begun, WP going low will have no effect on the write. See Table 3-2 for Write Protect Functionality Matrix.
2.6
Hold (HOLD)
2.2
Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock.
2.3
Serial Output (SO)
The SO pin is used to transfer data out of the 25xx040. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.
2.4
Serial Clock (SCK)
The SCK is used to synchronize the communication between a master and the 25xx040. Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input.
The HOLD pin is used to suspend transmission to the 25xx040 while in the middle of a serial sequence without having to re-transmit the entire sequence over at a later time. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high to low transition. The 25xx040 must remain selected during this sequence. The SI, SCK, and SO pins are in a high impedance state during the time the part is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line.
(c) 1997 Microchip Technology Inc.
Preliminary
DS21204A-page 5
25AA040/25LC040/25C040
3.0
3.1
FUNCTIONAL DESCRIPTION
PRINCIPLES OF OPERATION
3.3
Write Sequence
The 25xx040 is a 512 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today's popular microcontroller families, including Microchip's PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software. The 25xx040 contains an 8-bit instruction register. The part is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. The WP pin must be held high to allow writing to the memory array. Table 3-1 contains a list of the possible instruction bytes and format for device operation. The most significant address bit (A8) is located in the instruction byte. All instructions, addresses, and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25xx040 in `HOLD' mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted.
Prior to any attempt to write data to the 25xx040, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25xx040. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a write instruction, followed by the address, and then the data to be written. Keep in mind that the most significant address bit (A8) is included in the instruction byte. Up to 16 bytes of data can be sent to the 25xx040 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with XXXX 0000 and ends with XXXX 1111. If the internal address counter reaches XXXX 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS must be brought high after the least significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the status register may be read to check the status of the WIP, WEL, BP1, and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset.
3.2
Read Sequence
The part is selected by pulling CS low. The 8-bit read instruction with the A8 address bit is transmitted to the 25xx040 followed by the lower 8-bit address (A7 through A0). After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (01FFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1).
TABLE 3-1:
READ WRITE WRDI WREN RDSR WRSR Note: A8 is the
INSTRUCTION SET
Instruction Format 0000 A8011 0000 A8010 0000 0100 0000 0110 0000 0101 0000 0001 9th Description Read data from memory array beginning at selected address Write data to memory array beginning at selected address Reset the write enable latch (disable write operations) Set the write enable latch (enable write operations) Read status register Write status register
Instruction Name
address bit necessary to fully address 512 bytes.
DS21204A-page 6
Preliminary
(c) 1997 Microchip Technology Inc.
25AA040/25LC040/25C040
FIGURE 3-1:
CS 0 SCK instruction SI 0 0 0 0 A8 0 1 1 A7 6 lower address byte 5 4 3 2 1 A0 don't care data out 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
READ SEQUENCE
high impedance SO
FIGURE 3-2:
CS
BYTE WRITE SEQUENCE
twc 0 SCK instruction SI 0 0 0 0 A8 0 1 0 A7 6 lower address byte 5 4 3 2 1 A0 7 6 5 data byte 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
high impedance SO
FIGURE 3-3:
CS 0 SCK 1
PAGE WRITE SEQUENCE
2
3
4
5
6
7
8
9 10 11 13 14 15 16 17 18 19 20 21 22 23 24
instruction SI 0 0 0 0 A8 0 1 0 A7 6
lower address byte 5 4 3 2 1 0 7 6 5
data byte 1 4 3 2 1 0
CS 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SCK data byte 2 SI 7 6 5 4 3 2 1 0 7 6 data byte 3 5 4 3 2 1 0 7 data byte n (16 max) 6 5 4 3 2 1 0
(c) 1997 Microchip Technology Inc.
Preliminary
DS21204A-page 7
25AA040/25LC040/25C040
3.4 Write Enable (WREN) and Write Disable (WRDI)
The following is a list of conditions under which the write enable latch will be reset: * * * * * Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WP line is low
The 25xx040 contains a write enable latch. See Table 3-3 for the Write Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch.
FIGURE 3-4:
WRITE ENABLE SEQUENCE
CS 0 SCK 1 2 3 4 5 6 7
SI
0
0
0
0
0
1
1
0
high impedance SO
FIGURE 3-5:
WRITE DISABLE SEQUENCE
CS 0 SCK 1 2 3 4 5 6 7
SI
0
0
0
0
0
1
1 0
0
high impedance SO
DS21204A-page 8
Preliminary
(c) 1997 Microchip Technology Inc.
25AA040/25LC040/25C040
3.5 Read Status Register (RDSR) 3.6 Write Status Register(WRSR)
The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7 X 6 X 5 X 4 X 3 BP1 2 BP0 1 WEL 0 WIP The WRSR instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. The array is divided up into four segments. The user has the ability to write protect none, one, two, or all four of the segments of the array. The partitioning is controlled as illustrated in Table 3-2. See Figure 3-7 for WRSR timing sequence
The Write-In-Process (WIP) bit indicates whether the 25xx040 is busy with a write operation. When set to a `1' a write is in progress, when set to a `0' no write is in progress. This bit is read only. The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a `1' the latch allows writes to the array, when set to a `0' the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the status register. This bit is read only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write protected. These bits are set by the user issuing the WRSR instruction. These bits are non-volatile. See Figure 3-6 for RDSR timing sequence
TABLE 3-2:
BP1 0 0 1 1
ARRAY PROTECTION
BP0 0 1 0 1 Array Addresses Write Protected none upper 1/4 (0180h - 01FFh) upper 1/2 (0100h - 01FFh) all (0000h - 01FFh)
FIGURE 3-6:
READ STATUS REGISTER SEQUENCE
CS 0 SCK instruction SI 0 0 0 0 0 1 0 1 data from status register 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
high impedance SO
FIGURE 3-7:
WRITE STATUS REGISTER SEQUENCE
CS 0 SCK instruction SI 0 0 0 0 0 0 0 1 7 6 data to status register 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
high impedance SO
(c) 1997 Microchip Technology Inc.
Preliminary
DS21204A-page 9
25AA040/25LC040/25C040
3.7 Data Protection 3.8 Power On State
The following protection has been implemented to prevent inadvertent writes to the array: * The write enable latch is reset on power-up. * A write enable instruction must be issued to set the write enable latch. * After a byte write, page write, or status register write, the write enable latch is reset. * CS must be set high after the proper number of clock cycles to start an internal write cycle. * Access to the array during an internal write cycle is ignored and programming is continued. * The write enable latch is reset when the WP pin is low. The 25xx040 powers on in the following state: * * * * The device is in low power standby mode (CS= 1). The write enable latch is reset. SO is in high impedance state. A low level on CS is required to enter active state.
.
TABLE 3-3:
WP Low High High
WRITE PROTECT FUNCTIONALITY MATRIX
WEL X 0 1 Protected Blocks Protected Protected Protected Unprotected Blocks Protected Protected Writable Status Register Protected Protected Writable
DS21204A-page 10
Preliminary
(c) 1997 Microchip Technology Inc.
25AA040/25LC040/25C040
25AA040/25LC040/25C040 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. 25xx040 -- /P Package: P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead ST = TSSOP, 8-lead Blank = 0C to +70C I = -40C to +85C E = -40C to +125C 25AA040 25AA040T 25AA040X 25AA040XT 25LC040 25LC040T 25LC040X 25LC040XT 25C040 25C040T 25C040X 25C040XT 4096 bit 1.8V SPI Serial EEPROM 4096 bit 1.8V SPI Serial EEPROM Tape and Reel 4096 bit 1.8V SPI Serial EEPROM in alternate pinout (ST only) 4096 bit 1.8V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 4096 bit 2.5V SPI Serial EEPROM 4096 bit 2.5V SPI Serial EEPROM Tape and Reel 4096 bit 2.5V SPI Serial EEPROM in alternate pinout (ST only) 4096 bit 2.5V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only) 4096 bit 5.0V SPI Serial EEPROM 4096 bit 5.0V SPI Serial EEPROM Tape and Reel 4096 bit 5.0V SPI Serial EEPROM in alternate pinout (ST only) 4096 bit 5.0V SPI Serial EEPROM in alternate pinout Tape and Reel (ST only)
Temperature Range:
Devices:
Sales and Support
Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office. 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277. 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
(c) 1997 Microchip Technology Inc.
Preliminary
DS21204A-page 11
WORLDWIDE SALES & SERVICE
AMERICAS
Corporate Office
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All rights reserved. (c) 1997, Microchip Technology Incorporated, USA. 6/97 Printed on recycled paper.
M
Preliminary
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21204A-page 12
(c) 1997 Microchip Technology Inc.

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